1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit having electrical wiring layers for interconnecting semiconductor devices.
2. Description of the Related Art
Various attempts have been made to increase the operating speed performance of high density fine semiconductor integrated circuits. In the operating speed of semiconductor integrated circuits, total delay is divided into xe2x80x9cInterconnection Delayxe2x80x9d and xe2x80x9cIntrinsic Gate Delay.xe2x80x9d xe2x80x9cIntrinsic Gate Delayxe2x80x9d is caused by gates per se composed of transistors in the semiconductor integrated circuits whereas xe2x80x9cInterconnection Delayxe2x80x9d is caused by electrical wiring for connecting these transistors with each other. As shown in FIG. 13, the ratio of xe2x80x9cInterconnection Delayxe2x80x9d to xe2x80x9cIntrinsic Gate Delayxe2x80x9d is larger when the semiconductor integrated circuits become finer. xe2x80x9cInterconnection delayxe2x80x9d is affected by the capacitance and electrical resistance of on-chip interconnection.
As one of known approaches to enhance the performance of operating speed, there is a method of doping fluorine (F) or carbon (C) into an interlayer oxide film to reduce the relative dielectric constant of this interlayer oxide film per se, thereby improving the operation delay of integrated circuits due to the wiring capacitance. It has also been reported that it is effective to lower the density of the interlayer oxide film in order to reduce the relative dielectric constant thereof.
There is another known approach to employ a carbon-based material. The approach comprises the steps of forming a interlayer film and removing away the carbon-based interlayer film with oxygen (O2) plasma process.
There is a still another approach to reduce the effective or xe2x80x9cnetxe2x80x9d relative dielectric constant by providing a gap space within an interlayer film through adequate controlling of process conditions for fabricating the film.
As a result of the inventors"" investigation on the operating speed of semiconductor integrated circuits, the inventors have found the following problems.
In order to form fluorine-based oxide films with low dielectric constant, new dedicated chemical vapor deposition (CVD) apparatus is required. This new CVD apparatus is, however, different from the conventional CVD apparatus for use in forming interlayer films. For forming the desired films, the new CVD apparatus requires new precise growth processing conditions for forming films and the maintenance of these conditions. As far as fluorine-based silicon oxides are used for interlayer films, it remains difficult to reduce the relative dielectric constant less than 3.
The above-mentioned method of employing carbon-based material for the interlayer film also requires extra process facility including carbon-based interlayer film forming apparatus and dedicated O2-plasma apparatus.
Furthermore, in the method of forming interlayer films containing gaps or voids therein, it is difficult to precisely maintain the conditions for forming the films in CVD process. This difficulty results in the deviation of the film formation conditions, which in turn leads to chip defects such as short-circuit and breaking of electrical connection. Since these chip defects may occur after long-term use of IC chip products in some cases, this method cannot be used in view of the reliability of semiconductor integrated circuits.
It is, therefore, an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit capable of increasing its operation speed without the use of an additional process apparatus.
The present invention relates to a method of manufacturing a semiconductor integrated circuit having, on a substrate, conductors for electrically connecting semiconductor devices to each other. The substrate has, on its one main surface, a first region and a second region that is different from the first region. This method comprises the steps of: (a)forming a plurality of semiconductor devices on a substrate; (b)forming an etching stopper film on said plurality of semiconductor devices; (c) forming a first conducting portion for connecting said plurality of semiconductor devices with each other; (d) forming, on said etching stopper film, an interlayer dielectric film portion and a second conducting portion for connection of said first conducting portion in said first region, said interlayer dielectric film portion containing silicon oxide; (e) forming an opening in said second region through said interlayer dielectric film portion; and (f) etching said interlayer dielectric film portion having said opening formed therein in an etching solution containing at least hydrogen fluoride acid to remove said interlayer dielectric film portion.
The interlayer film portion includes a silicon-based dielectric film such as silicon oxide film. When the silicon-based interlayer film portion is removed using silicon oxide film dissolvable solution, the etching stopper layer serves as a protective layer against the etching of the silicon-based interlayer film portion. This etching stopper film can protect the semiconductor devices covered therewith against any unwanted etching treatment. Since the opening is formed in the second region that does not have the second conducting portion blocking the opening, the opening can reach the etching stopper film. As the interlayer film is exposed on the inner side surface of the opening, etching process starts from the interlayer film exposed on all the inner side surface of the opening.
The present invention may include one or more process steps as follows.
In the method of manufacturing a semiconductor integrated circuit in accordance with the present invention, step (c) includes the step of (c1) forming contacting conductors that directly connect with said semiconductor devices and wiring conductors. The wiring conductors are connected to the contacting conductors. The first conducting portion includes said contacting conductors and said wiring conductors.
In the method of manufacturing a semiconductor integrated circuit according to the present invention, step (d) includes the step of (d1) forming one or more wiring conductors, a silicon oxide film on each of said wiring conductors and said first conducting portion, and via conductors in said silicon oxide film. The second conducting portion includes said wiring conductors and said via conductors, and the interlayer dielectric film portion includes said silicon oxide film.
In addition, the wiring conductors may contain copper as its main constituent material whereas the via conductors and said contact conductors may contain tungsten as main constituent material thereof.
In the method of manufacturing a semiconductor integrated circuit according to the invention, the second conducting portion in the interlayer dielectric film portion may be formed in a damascene method in step (d). The damascene method indicates a dual-damascene method or a single-damascene method.
According to the damascene methods, the fabrication procedure begins with the step of forming a silicon oxide film provided so as to cover underlying conductors. Then, depressed portions are formed in this silicon oxide film so as to reach the underlying conductors, and other conductors to are formed in these depressed portions. The other conductors may be composed of the via conductors and/or wiring conductors. The depressed portions indicate at least one of first and second depressed portions. The first depressed portions are filled with the via conductors and the second depressed portions are filled with the wiring conductors. These via conductors and wiring conductors may be formed in the same process step.
The second conducting portion may include one or more, conducting levels, each being composed of the wiring conductors and via conductors. The interlayer film portion may include a specific number of silicon-based dielectric layers, the number of which is two times that of the conducting levels. Alternatively, the second conducting portion may include one or more conducting layers, each being composed of wiring conductor portions and via conductor portions.
The interlayer film portion includes one or more silicon-based dielectric layers, the number of which are equal to that of the conducting layers.
In the method of manufacturing a semiconductor integrated circuit in accordance with the present invention, the etching stopper film may be formed over the first conducting portion in step (b). The etching stopper film can protect the first conducting portion provided thereunder from etchant. The first conducting portion may be provided anywhere independently of the location of the opening. Additionally, the first conducting portion disposed under the etching stopper film may be made of material that can be etched in the etchant. The first conducting portion comprises any given number of wiring layers.
In the method of manufacturing a semiconductor integrated circuit according to the present invention, the first conducting portion may be formed in step (c) so as to pass through the etching stopper film and so as to connect the semiconductor devices with each other. This configuration is advantageous to an application that a silicon nitride film is used inherently as the etching stopper film for forming self-align contact structure.
In the method of manufacturing a semiconductor integrated circuit according to the present invention, the substrate may include a plurality of semiconductor chip regions and a scribe region. Each of the plurality of semiconductor chip regions includes semiconductor integrated circuits, and the scribe region is provided so as to surround respective semiconductor chip regions. In the substrate thus arranged, step (e) may comprise the step of forming said opening in the scribe region and/or the semiconductor chip regions.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.